FIG. 4 is a block diagram showing a function test algorithmic pattern generator of a prior art semiconductor test device. In FIG. 4, the reference numeral 1 designates a base data register for storing reference data. The reference numeral 2 designates a constant register for storing a constant to be used in the constant operation. The reference numeral 3a designates an arithmetical and logical operation unit for conducting various arithmetical and logical operations. The reference numeral 4 designates a selector for selecting the input of the ALU 3a. The reference numeral 5 designates an ALU output register for storing the operation result of the ALU 3a.
The device will be operated as follows.
When the output of the base data register 1 is selected by the selector 4, this output is provided as input to the ALU 3a, and is subjected to arithmetical and logical operation with using a constant which is supplied from the constant register 2. The operation result is stored at the ALU output register 5. On the other hand, when the output of-the ALU output register 5 is selected by the selector 4, that output is subjected to the above-described arithmetical and logical operation using the constant from the constant register 2, and the operation result is stored at the ALU output register 5. Thus, the content of the ALU output register 5 is renewed successively.
In the prior art algorithmic pattern generator with such a construction, arithmetical and logical operations which can be executed in the ALU are limited to those such as addition, subtraction, shifting, inversion, AND, and OR. This requires many types of fundamental operations to generate a complicated pattern such as a pseudo-random number sequence, which results in an incapability in conducting a high speed test.